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Computer Architecture - OVERVIEW decimal value = (-1)S × (0.significand)" xmpDM:startTime="441233" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="× bexponent exponent = characteristic – b(y – 1) – x y y-1 x x-1 0 S characteristic characteristic characteristic" xmpDM:startTime="441233" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="significand significand significand" xmpDM:startTime="441233" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Representable number range TI II - Computer Architecture - OVERVIEW a) b) c) underflow overflow 0 -231 231-1 - (1-2-23)·2127" xmpDM:startTime="468833" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="(1-2-23) ·2127 - 0.5" xmpDM:startTime="468833" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="·2-128 0.5" xmpDM:startTime="468833" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="·2-128 - (1-2-24)·2127 (1-2-24) ·2127 - 0.5" xmpDM:startTime="468833" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="·2-128 0.5" xmpDM:startTime="468833" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="·2-128 overflow" xmpDM:startTime="468833" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Overview of the 64 bit IEEE format TI II - Computer Architecture - OVERVIEW characteristic number remark 0 (-1)S 0.significand" xmpDM:startTime="497167" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="· 2 -1022 subnormal 1 (-1)S 1.significand" xmpDM:startTime="497167" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="· 2 -1022 … (-1)S 1.significand" xmpDM:startTime="497167" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="· 2 characteristic – 1023 2046 (-1)S 1.significand" xmpDM:startTime="497167" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="· 2 1023 2047 significand = 0: (-1)S  overflow 2047 significand ≠ 0: NaN not a number" xmpDM:startTime="497167" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Carry-lookahead adder TI II - Computer Architecture - OVERVIEW  3 2 1 0 3 2 1 0 CI CO" xmpDM:startTime="511500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="3 2 1 0 P Q   3 2 1 0 3 2 1 0 CI CO 3 2" xmpDM:startTime="511500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="1 0 P Q  0 a b s 0 3 4 7 a a a b b b s" xmpDM:startTime="511500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="s s s s s s 0 3 4 7 0 1 2 3 4 5 6 7 - -" xmpDM:startTime="511500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="- - c Cascading two 4 bit carry-lookahead adders to add 8 bit integers" xmpDM:startTime="511500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Subtractor We can use an adder, take the minuend X as it is, invert the single bits of the subtrahend" xmpDM:startTime="533867" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Y, and set the carry in CI." xmpDM:startTime="533867" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="TI II - Computer Architecture - OVERVIEW 1  0 1 2 3 0 1 2 3 C I C" xmpDM:startTime="533867" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="O 0 1 2 3 P Q  1 1 1 1 X Y X - Y Subtraction of two" xmpDM:startTime="533867" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="numbers in two‘s complement format." xmpDM:startTime="533867" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="" xmpDM:startTime="533867" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Example 2: 32 - 3.75" xmpDM:startTime="540500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="= 28 using 4 significands, base = 2 1.000" xmpDM:startTime="540500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="* 25 - 1.111" xmpDM:startTime="540500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="* 21 “Infinite” internal precision 1.000" xmpDM:startTime="540500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="0000 * 25 -0.000" xmpDM:startTime="540500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="1111 * 25 align, keep all the bits 0.111" xmpDM:startTime="540500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="0001 * 25 precise result (= 28.25)" xmpDM:startTime="540500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="1.110" xmpDM:startTime="540500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="0010 * 24 normalized 1.110" xmpDM:startTime="540500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="* 24 round down (= 28) Using g(uard), r(ound), s(ticky) bits plus 4 significands 1.000" xmpDM:startTime="540500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="000 * 25 -0.000" xmpDM:startTime="540500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="111 * 25 align, drop bit, set sticky 0.111" xmpDM:startTime="540500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="001 * 25 1.110" xmpDM:startTime="540500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="01 * 24 normalized 1.110" xmpDM:startTime="540500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="* 24 round down (= 28) TI II - Computer Architecture - OVERVIEW" xmpDM:startTime="540500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Diagram of a simple ALU TI II - Computer Architecture - OVERVIEW register X register Y multiplexer ALU1 ALU2 arithmetic" xmpDM:startTime="559733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="logic combinational circuit ALU3 shifter register Z cout over- flow sign zero s7 s6 s5 s4 s3 s2 s1 cin" xmpDM:startTime="559733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="s1 s2 ALU1 ALU2 0 0 X Y 0 1 X 0 1 0 Y 0 1 1 Y X" xmpDM:startTime="559733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="s6 s7 Z 0 0 ALU3 0 1 ALU3  2 1 0 ALU3  2 1 1 store Z" xmpDM:startTime="559733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="s3 s4 s5 ALU3 0 0 0 ALU1 + ALU2 +cin 0 0 1 ALU1 – ALU2 – Not(cin) 0" xmpDM:startTime="559733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="1 0 ALU2 – ALU1 – Not(cin) 0 1 1 ALU1  ALU2 1 0 0 ALU1  ALU2 1" xmpDM:startTime="559733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="0 1 Not(ALU1)  ALU2 1 1 0 ALU1  ALU2 1 1 1 ALU1  ALU2" xmpDM:startTime="559733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Content Introduction Single Processor Systems Historical overview Six-level computer architecture Data representation and Computer arithmetic Data and number representation Basic" xmpDM:startTime="576233" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="arithmetic Microarchitecture Microprocessor architecture Microprogramming Pipelining Instruction Set Architecture CISC vs." xmpDM:startTime="576233" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="RISC Data types, Addressing, Instructions Assembler Memories Hierarchy, Types Physical &amp; Virtual Memory Segmentation &amp; Paging Caches TI II -" xmpDM:startTime="576233" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Computer Architecture - OVERVIEW" xmpDM:startTime="576233" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Internal architecture of a simple and simplified microprocessor TI II - Computer Architecture - OVERVIEW registers execution unit control unit" xmpDM:startTime="586200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="system bus interface execution unit address generation, load store, branch execution, memory management arithmetic logic unit floating point unit data" xmpDM:startTime="586200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="bus buffer address bus buffer controller, decoder control register status register operand register opcode registers clock address bus data bus" xmpDM:startTime="586200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="control bus status signals control signals system clock reset VCC GND" xmpDM:startTime="586200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Pipelining TI II - Computer Architecture - OVERVIEW 1." xmpDM:startTime="618500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Instruction instruction fetch execution write back result instruction decode operand fetch Sequential execution: instruction fetch instruction decode ." xmpDM:startTime="618500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="." xmpDM:startTime="618500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="." xmpDM:startTime="618500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="2." xmpDM:startTime="618500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Instruction instruction fetch execution write back result instruction decode operand fetch 1." xmpDM:startTime="618500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Instruction Pipelining: instruction fetch execution write back result instruction decode operand fetch 2." xmpDM:startTime="618500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Instruction instruction fetch execution write back result instruction decode operand fetch 3." xmpDM:startTime="618500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Instruction" xmpDM:startTime="618500" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Three types of pipeline hazards Data hazards arise because of the unavailability of an operand For example, an instruction may" xmpDM:startTime="651733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="require an operand that will be the result of a preceding, still uncompleted instruction." xmpDM:startTime="651733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Structural hazards may arise from some combinations of instructions that cannot be accommodated because of resource conflicts For example, if" xmpDM:startTime="651733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="the processor has only one register file write port and two instructions want to write in the register file at" xmpDM:startTime="651733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="the same time." xmpDM:startTime="651733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Control hazards arise from branch, jump, and other control flow instructions For example, a taken branch interrupts the flow of" xmpDM:startTime="651733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="instructions into the pipeline  the branch target must be fetched before the pipeline can resume execution." xmpDM:startTime="651733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Common solution is to stall the pipeline until the hazard is resolved, inserting one or more “bubbles” in the pipeline." xmpDM:startTime="651733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="TI II - Computer Architecture - OVERVIEW" xmpDM:startTime="651733" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Bypass techniques TI II - Computer Architecture - OVERVIEW Operand register B Operand register A ALU Result register Internal Data" xmpDM:startTime="696233" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="bus Control lines from the control unit Bypass 1 Registers Bypass 2 Load forwarding from cache or main memory Result" xmpDM:startTime="696233" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="forwarding" xmpDM:startTime="696233" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Two-bit Predictors (Hysteresis Scheme) TI II - Computer Architecture - OVERVIEW Predict Strongly Not Taken 00 Predict Weakly Not Taken" xmpDM:startTime="709367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="01 Predict Weakly Taken 10 Predict Strongly Taken 11 Taken Not Taken Taken Not Taken Taken Not Taken Taken Not" xmpDM:startTime="709367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Taken Realization: Intel XScale, Sun UltraSPARC IIi" xmpDM:startTime="709367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Performance of branch handling techniques TI II - Computer Architecture - OVERVIEW Class Technique Rough Accuracy (Spec 89) Static always" xmpDM:startTime="739200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="not taken 40% Static always taken 60% Static backward taken, forward not taken 65% Software Static analysis 70% Software Profiling" xmpDM:startTime="739200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="75% Dynamic 1-bit 80% Dynamic 2-bit 93% Dynamic two-level adaptive 95 – 97.5%" xmpDM:startTime="739200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Adapted from: Dave Archer, Branch Prediction: Introduction and Survey, 2007" xmpDM:startTime="739200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Pipelining basics: Summary Hazards limit performance Structural hazards: need more HW resources Data hazards: need detection and forwarding Control hazards:" xmpDM:startTime="749867" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="early evaluation, delayed branch, prediction Compilers may reduce cost of data and control hazards Compiler Scheduling Branch delay slots Static" xmpDM:startTime="749867" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="branch prediction Increasing length of pipe increases impact of hazards Pipelining helps instruction bandwidth, not latency Multi-cycle operations (floating-point) and" xmpDM:startTime="749867" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="interrupts make pipelining harder TI II - Computer Architecture - OVERVIEW" xmpDM:startTime="749867" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Sections of a Superscalar Pipeline The ability to issue and execute instructions out-of-order partitions a superscalar pipeline in three distinct" xmpDM:startTime="767600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="sections in-order section with the instruction fetch, decode and rename stages - the issue is also part of the in-order" xmpDM:startTime="767600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="section in case of an in-order issue, out-of-order section starting with the issue in case of an out-of-order issue processor," xmpDM:startTime="767600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="the execution stage, and usually the completion stage, and again an in-order section that comprises the retirement and write-back stages." xmpDM:startTime="767600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="TI II - Computer Architecture - OVERVIEW Fig functional units Instruction Fetch" xmpDM:startTime="767600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Example: Dynamic Scheduling for a FP-Unit using Tomasulo’s Algorithm TI II - Computer Architecture - OVERVIEW Instruction Queue from ID" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Unit ID RS Value F0 Add2 0.0" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="F1 1.0" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="F2 2.0" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="F3 Add1 3.0" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="FP Registers ID op RS1 Val1 RS2 Val2 busy Add3 0 Add2 - 0 1.0" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="0 2.0" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="1 Add1 + Mul1 n/a 0 2.0" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="1 ID op RS1 Val1 RS2 Val2 busy Mul2 0 Mul1 * 0 1.0" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="0 2.0" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="1 Reservation Stations of FP Adder Reservation Stations of FP Multiplier FP Adder FP Multiplier FP Operation Bus Common Data" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Bus (CDB) MUL.D" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="F0,F1,F2 ADD.D" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="F3,F0,F2 SUB.D" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="F0,F1,F2 with MUL.D" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="F0,F1,F2  F0=F1*F2 Operand Busses" xmpDM:startTime="805100" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Content Introduction Single Processor Systems Historical overview Six-level computer architecture Data representation and Computer arithmetic Data and number representation Basic" xmpDM:startTime="829833" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="arithmetic Microarchitecture Microprocessor architecture Microprogramming Pipelining Instruction Set Architecture CISC vs." xmpDM:startTime="829833" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="RISC Data types, Addressing, Instructions Assembler Memories Hierarchy, Types Physical &amp; Virtual Memory Segmentation &amp; Paging Caches TI II -" xmpDM:startTime="829833" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Computer Architecture - OVERVIEW" xmpDM:startTime="829833" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Limitations of CISC architectures Usage of instructions (80/20 rule) Only 20% of the instructions used frequently Many powerful instructions (rarely" xmpDM:startTime="858533" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="used) Complex instruction format(s) Micro programming Critical problem: number of cycles per instruction (CPI) Many classical CISC architectures have CPI" xmpDM:startTime="858533" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="&gt;&gt; 2 Motorola MC68030: CPI = 4-6 Intel 80386: CPI = 4-5 BUT: optimized code for Pentium/Itanium/… – typical CPI" xmpDM:startTime="858533" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="≈ 1 Superscalar processors e.g." xmpDM:startTime="858533" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="issuing 4 instructions in parallel could theoretically go down to 0.25," xmpDM:startTime="858533" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="but: floating-point, SIMD, branch mis-predictions, memory latency … TI II - Computer Architecture - OVERVIEW" xmpDM:startTime="858533" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Reduced Instruction Set Computer (RISC) The instruction set consists of a few, absolutely necessary instructions (≤ 128) and instruction formats" xmpDM:startTime="879633" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="(≤ 4) with a fixed instruction length of 32 bit and only some addressing modes (≤ 4)." xmpDM:startTime="879633" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="This allows a much simpler implementation of the control unit and saves space on the chip for additional units." xmpDM:startTime="879633" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Many general-purpose registers, at least 32, are needed." xmpDM:startTime="879633" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Memory access is only possible via special load and store instructions." xmpDM:startTime="879633" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="TI II - Computer Architecture - OVERVIEW" xmpDM:startTime="879633" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Addressing modes – some examples Be aware: Naming may differ depending on the architecture Not all processors support all modes" xmpDM:startTime="895600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Absolute/direct: jmpa address  PC := address PC relative: jmpo offset  PC := PC’ + offset Register indirect: jmpr" xmpDM:startTime="895600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="R  PC := R Sequential execution: nop  PC := PC’ Register (direct): mul R1,R2,R3  PC := PC’;" xmpDM:startTime="895600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="R1 := R2*R3 Base plus offset: load R1,R2,val  PC := PC’; R1 := mem(R2 + val) Immediate: add R1,R2,val" xmpDM:startTime="895600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name=" PC := PC’; R1 := R2 + val Implicit: load x  PC := PC’; accumulator := x Indexed" xmpDM:startTime="895600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="absolute, base plus index (plus offset), scaled, autoincrement/-decrement, … See https://en.wikipedia.org/wiki/Addressing_mode" xmpDM:startTime="895600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="TI II - Computer Architecture - OVERVIEW" xmpDM:startTime="895600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Procedures, Traps, Interrupts &amp; Co." xmpDM:startTime="927767" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Many reasons for non-linear program execution Jumps, branches Procedure calls, subroutines, method invocation Multithreading, parallel processes, co-routines Hardware interrupts (processor" xmpDM:startTime="927767" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="external reasons) Traps, software interrupts (processor internal reasons) Non linear program execution is the normal case! And invalidates standard cache" xmpDM:startTime="927767" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="content ..." xmpDM:startTime="927767" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Trace caches can help (more later) TI II - Computer Architecture - OVERVIEW" xmpDM:startTime="927767" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Example: Calculation of the start address of an Interrupt Service Routine (ISR) TI II - Computer Architecture - OVERVIEW ISR" xmpDM:startTime="951000" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Memory Interrupt Vector Table Start Address Base Address Interrupt Source Int." xmpDM:startTime="951000" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Vector Number x 2, 4, … Scaling Data Bus INT INTA + Address Bus Base Address Register" xmpDM:startTime="951000" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Compiler vs." xmpDM:startTime="979600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Assembler Assembler Source: symbolic representation of a machine language (assembly language) Destination: numerical representation of the machine language (instructions from" xmpDM:startTime="979600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="ISA) Examples: inline assembler in Visual Studio, MASM, ilasm, asm (gcc, Linux), MMIXal, nasm, ..." xmpDM:startTime="979600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Compiler Source: high-level language (depends on the definition of „high“ ...)," xmpDM:startTime="979600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="e.g.," xmpDM:startTime="979600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="C, Java, C#, Cobol, Modula, C++, ..." xmpDM:startTime="979600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Destination: assembler language or (built-in assembler) numerical representation of the machine language (instructions from ISA) Examples: C#-Compiler in Visual Studio," xmpDM:startTime="979600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="gcc, cc, javac, ..." xmpDM:startTime="979600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Assembler language Pure assembler language: 1:1 mapping onto ISA instructions But additionally: symbolic names, addresses, labels TI II - Computer" xmpDM:startTime="979600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Architecture - OVERVIEW" xmpDM:startTime="979600" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Generation of an executable binary program TI II - Computer Architecture - OVERVIEW" xmpDM:startTime="989900" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Content Introduction Single Processor Systems Historical overview Six-level computer architecture Data representation and Computer arithmetic Data and number representation Basic" xmpDM:startTime="1001800" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="arithmetic Microarchitecture Microprocessor architecture Microprogramming Pipelining Instruction Set Architecture CISC vs." xmpDM:startTime="1001800" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="RISC Data types, Addressing, Instructions Assembler Memories Hierarchy, Types Physical &amp; Virtual Memory Segmentation &amp; Paging Caches TI II -" xmpDM:startTime="1001800" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Computer Architecture - OVERVIEW" xmpDM:startTime="1001800" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Memory hierarchy TI II - Computer Architecture - OVERVIEW Increasing cost per byte Decreasing capacity Decreasing access time Register On-Chip-Cache" xmpDM:startTime="1020333" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Secondary level Cache (SRAM) Main memory (DRAM) Secondary memory (Hard disks) Archive memory (Tapes, disks)" xmpDM:startTime="1020333" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Cache Architecture (high level) The cache comprises a (relatively) small but fast memory plus a controller." xmpDM:startTime="1072633" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="It stores with a high probability copies of those parts of the main memory the CPU will access in the" xmpDM:startTime="1072633" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="near future." xmpDM:startTime="1072633" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="In the ideal case the controller swaps these copies into the cache before the CPU wants to read them to" xmpDM:startTime="1072633" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="avoid wait cycles." xmpDM:startTime="1072633" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="TI II - Computer Architecture - OVERVIEW mP Memory Cache memory Controller Address bus Data bus Control bus Read/write Swap" xmpDM:startTime="1072633" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="in/out" xmpDM:startTime="1072633" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Associativity Number of block frames per set The total number c of block frames in a cache is the product" xmpDM:startTime="1087700" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="of the number s of sets and the associativity n, thus c = s * n." xmpDM:startTime="1087700" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="A cache is called fully associative, if it consists of a single set only (s = 1, n = c)" xmpDM:startTime="1087700" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="direct mapped, if each set consists of a single frame only (n = 1, s = c) n-way set associative," xmpDM:startTime="1087700" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="otherwise (s = c / n) TI II - Computer Architecture - OVERVIEW n n n Cache memory Set 1" xmpDM:startTime="1087700" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Set 2 Set s" xmpDM:startTime="1087700" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Basic idea of virtual memory management TI II - Computer Architecture - OVERVIEW CPU Main memory Background memory Working sets" xmpDM:startTime="1120367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Programs and data Process 2 swapping, paging Process 1" xmpDM:startTime="1120367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Challenges for the virtual memory management Two main challenges for the swapping of data between main memory and background memory" xmpDM:startTime="1149367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="1." xmpDM:startTime="1149367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="When to swap a page? When is the best point in time to swap a page into main memory? Common" xmpDM:startTime="1149367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="approach On demand paging Swap a page into main memory as soon as a process tries to access data stored" xmpDM:startTime="1149367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="on this page The access to data located on a page that is currently not stored in the main memory" xmpDM:startTime="1149367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="is called a page fault." xmpDM:startTime="1149367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Page faults cause an interrupt that triggers the OS to suspend the faulting process and to swap the required page" xmpDM:startTime="1149367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="into main memory." xmpDM:startTime="1149367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="TI II - Computer Architecture - OVERVIEW" xmpDM:startTime="1149367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Challenges for the virtual memory management 2." xmpDM:startTime="1169367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Which page to replace? In case of a full main memory, which page should the OS replace to free some" xmpDM:startTime="1169367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="space for a new page? The most common approaches: FIFO (first-in-first-out): Replace the oldest page LIFO (last-in-first-out): Replace the newest" xmpDM:startTime="1169367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="page LRU (least recently used): Replace the page that has not been referenced for the longest time LFU (least frequently" xmpDM:startTime="1169367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="used): Replace the page with the lowest number of references LRD (least reference density): Mixture of LRU and LFU –" xmpDM:startTime="1169367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="replace the page with the lowest ratio of references / age of page in main memory Random: As the name" xmpDM:startTime="1169367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="indicates – replace an arbitrary page https://en.wikipedia.org/wiki/Page_replacement_algorithm" xmpDM:startTime="1169367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Additionally, favor unchanged pages No writing back required! TI II - Computer Architecture - OVERVIEW" xmpDM:startTime="1169367" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Location of cache and memory management unit Two possible ways for the integration of a cache using virtual memory management:" xmpDM:startTime="1191067" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Virtual cache The cache is located between the CPU and the MMU and operates on virtual addresses, i.e.," xmpDM:startTime="1191067" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="the cache uses the more significand bits of the virtual address as tags." xmpDM:startTime="1191067" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="TI II - Computer Architecture - OVERVIEW CPU Cache MMU Main memory Data Virtual address Physical address" xmpDM:startTime="1191067" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Configurations TI II - Computer Architecture - OVERVIEW Processor Processor Interconnect Shared memory Global memory Physically distributed memory Distributed address" xmpDM:startTime="1223867" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="space Shared address space Empty Processor Processor Interconnect Local memory Local memory Symmetric multiprocessor Distributed shared memory multiprocessor Prozessor Prozessor" xmpDM:startTime="1223867" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Interconnect Local memory Local memory send receive Message passing (shared nothing) multiprocessor" xmpDM:startTime="1223867" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Classification of interconnects static Interconnect dynamic One dimensional Two dimensional Bus Crossbar switch Banyan network Three dimensional N- dimensional TI" xmpDM:startTime="1265700" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="II - Computer Architecture - OVERVIEW … …" xmpDM:startTime="1265700" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="The cache coherence problem What happens if several components read and write the content of the same addresses in main" xmpDM:startTime="1276200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="memory and/or caches? Which write is valid? What to read after several writes? Does this depend on the memory or" xmpDM:startTime="1276200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="cache? Coherence Defines the behavior of reads and writes to a single address (word, variable, memory location) The computer system" xmpDM:startTime="1276200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="has to proceed in a deterministic way by guaranteeing that each read operation always fetches the most current update of" xmpDM:startTime="1276200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="the content at a single address location." xmpDM:startTime="1276200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Outdated content, eventually stored in a cache or main memory, must not be used! However, the content of a single" xmpDM:startTime="1276200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="address location stored at several caches and the main memory may be inconsistent (as long as no processor reads this" xmpDM:startTime="1276200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="data…) https://en.wikipedia.org/wiki/Cache_coherence" xmpDM:startTime="1276200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Consistency A memory system is consistent if all copies of the content of a single address are identical at all" xmpDM:startTime="1276200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="locations (i.e." xmpDM:startTime="1276200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="all caches and the main memory) This guarantees coherence, but at a high effort … TI II - Computer Architecture" xmpDM:startTime="1276200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="- OVERVIEW" xmpDM:startTime="1276200" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="MESI example TI II - Computer Architecture - OVERVIEW Exclusive unmodified Shared unmodified P1 P2 Main memory ld 4711 5" xmpDM:startTime="1321133" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="4711 5 ld 4711 Shared unmodified 5 RME RMS SHR st 4711 WH SHW Invalid Exclusive modified 1 ld 4711" xmpDM:startTime="1321133" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="RMS SHR 1 4711 Shared unmodified 1 Shared unmodified Read hit Read miss, shared Read miss, exclusive Write hit Write" xmpDM:startTime="1321133" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="miss Snoop hit on a read Snoop hit on a write or read-with-intent-to modify RH RMS RME WH WM SHR" xmpDM:startTime="1321133" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="SHW" xmpDM:startTime="1321133" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Content Introduction Single Processor Systems Historical overview Six-level computer architecture Data representation and Computer arithmetic Data and number representation Basic" xmpDM:startTime="1344233" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="arithmetic Microarchitecture Microprocessor architecture Microprogramming Pipelining Instruction Set Architecture CISC vs." xmpDM:startTime="1344233" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="RISC Data types, Addressing, Instructions Assembler Memories Hierarchy, Types Physical &amp; Virtual Memory Segmentation &amp; Paging Caches TI II -" xmpDM:startTime="1344233" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Computer Architecture - OVERVIEW All slides (pptx and pdf), videos, Q&amp;A sessions available at: www.jochenschiller.de" xmpDM:startTime="1344233" xmpDM:duration="1000"/></rdf:li><rdf:li><rdf:Description xmpDM:name="" xmpDM:startTime="1344233" xmpDM:duration="1000"/></rdf:li></rdf:Seq>
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75, 47"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Subtractor" xmpDM:startTime="533867" tscDM:image="TI_II_Overview_Thumbnails.png" tscDM:imageindex="18" tscDM:imageoffset="0" tscDM:imagerect="1350, 0, 75, 47"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Example 2: 32 - 3.75 = 28 using 4 significands, base = 2" xmpDM:startTime="540500" tscDM:image="TI_II_Overview_Thumbnails.png" tscDM:imageindex="19" tscDM:imageoffset="0" tscDM:imagerect="1425, 0, 75, 47"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Diagram of a simple ALU" xmpDM:startTime="559733" tscDM:image="TI_II_Overview_Thumbnails.png" tscDM:imageindex="20" tscDM:imageoffset="0" tscDM:imagerect="1500, 0, 75, 47"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Content" xmpDM:startTime="576233" tscDM:image="TI_II_Overview_Thumbnails.png" tscDM:imageindex="21" tscDM:imageoffset="0" tscDM:imagerect="1575, 0, 75, 47"/></rdf:li><rdf:li><rdf:Description xmpDM:name="Internal architecture of a simple and simplified microprocessor" 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